1. Field of the Invention
The present invention relates to the fabrication of integrated circuits and to a process and apparatus for forming semiconductor devices on a substrate.
2. Background of the Related Art
Consistent and fairly predictable improvement in integrated circuit (IC) design and fabrication has been observed in the last decade. One key to successful improvements in IC design and fabrication is the multilevel interconnect technology which provides the conductive paths in an IC device. The shrinking dimensions of conductive or semiconductive substrate features such as horizontal lines and vertical contacts, vias, or interconnects, in very large scale integration (VLSI) and ultra large scale integration (ULSI) technology, has increased the importance of improving the current density of semiconductor devices.
In order to further improve the current density of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and low dielectric constant (low k) materials (defined herein as having dielectric constants, k, less than about 4.0) as insulating layers to reduce the capacitive coupling between adjacent interconnects. Increased capacitative coupling between layers can detrimentally affect the functioning of semiconductor devices.
However, typical low k dielectric materials are generally porous and generally require a barrier layer to prevent interlayer diffusion of materials into the low k dielectric materials. The barrier layer comprises conventional barrier materials, such as silicon oxide and silicon nitride, that have dielectric constants greater than 4.0 and often greater than 7.0. The resulting insulator stack of low k dielectric materials and conventional barrier materials may have a dielectric constant that is not much below 6.0 which minimizes the use of low k dielectric materials as intermetal dielectric layers.
Copper is also being used to improve the current density of semiconductor devices. Copper (Cu) is becoming the interconnect material of choice because of copper""s low resistivity (1.7 xcexcxcexa9-cm) and high current carrying capacity. However, copper diffuses more readily into surrounding materials and can alter the electronic device characteristics of the adjacent layers and, for example, form a conductive path between layers, thereby reducing the reliability of the overall circuit and may even result in device failure.
One additional difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieving precise pattern etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Further, the etch processes of low k materials, such as silicon carbide (SiC) and carbon doped silicon oxides, have not been well quantified and qualified in the art Thus, the combination of low k materials and copper has led to new deposition methods for preparing semiconductor features, such as vertical and horizontal interconnects, since copper is not easily etched to form metal lines. One method is the damascene or dual damascene methods depositing vertical and horizontal interconnects, wherein one or more dielectric materials are deposited and pattern etched to form the vertical and horizontal interconnects. Conductive materials, such as copper and other metals, are then inlaid into the etched pattern and any excess metal is removed from the top of the structure in a planarization process, such as chemical mechanical polishing (CMP).
However, low k dielectric materials often have a less than desirable hardness. Hardness is defined herein as a stability of a material during processing for retention of its shape or form. If low k dielectric materials disposed adjacent the dual damascene structure lacks sufficient hardness, the dual damascene structures may be imprecisely formed and can deform during latter processing of the substrate. For example, CMP can exert force against the dielectric material disposed on the substrate surface, which can distort the dielectric material, and in some cases result in delamination of the dielectric material from the substrate. Also, the low k dielectric materials are porous and processing, such as chemical mechanical polishing, can compress the porous dielectric material and increase the k value.
Additionally, it has been observed that dual damascene structures formed in low k materials have greater mechanical stresses than structures formed in traditional dielectric materials. Greater mechanical stresses can lead to imprecise formation of the dual damascene structure and increased deformation of the dual damascene structure during processing. Deformation or malformation of the dual damascene structures can detrimentally affect the performance of semiconductor devices.
Therefore, there is a need for an improved process for forming dual damascene structures with low k dielectric material. Ideally the low k dual damascene structure has good hardness and can be formed without the presence of barrier layers or etch-stops.
The invention generally relates to a method and apparatus for processing a substrate to form a feature in low k dielectric materials. One aspect of the invention provides a method for forming a feature in a low k dielectric material including forming a feature definition in a dielectric material deposited on a surface of a substrate, depositing one or more conductive materials to fill at least a portion of the feature definition, planarizing the substrate surface to expose the dielectric material, removing at least a portion of the dielectric material, and depositing a low k dielectric material.
Another aspect of the invention provides a method for forming a dual damascene interconnect comprising depositing one or more dielectric layers on a substrate, etching the one or more dielectric layers to form the dual damascene definition, the dual damascene definition having a vertical and a horizontal interconnect, depositing a conductive barrier layer over the exposed services of a dual damascene definition, depositing a conductive material over the conductive barrier layer to fill at least a portion of the dual damascene definition, planarizing the filled dual damascene definition to expose the one or more dielectric layers, removing at least a portion of the one or more dielectric layers, depositing a low k dielectric material, and depositing a self-planarizing dielectric material on the low k dielectric layer.
Another aspect of the invention provides a method for forming a dual damascene interconnect, comprising depositing a first dielectric material, depositing a second dielectric material on the first dielectric material, etching the second dielectric layer to exposed a portion of the first dielectric layer, depositing a third dielectric layer on the second dielectric material and exposed portion of the first dielectric layer, etching the first and third dielectric layers to form a vertical interconnect and a horizontal interconnect of a dual damascene definition, depositing a conductive barrier layer over exposed surfaces of the dual damascene definition, depositing a conductive material over the conductive barrier layer to fill at least a portion of the dual damascene definition, planarizing the filled dual damascene definition to expose the one or more dielectric layers, removing the one or more dielectric layers, depositing a low k dielectric material on the substrate, and depositing a self-planarizing dielectric layer on the low k dielectric material.